修复mem被阻塞时读数据错误问题
This commit is contained in:
parent
5bd7124535
commit
ca1a6abe7b
|
@ -6,4 +6,5 @@
|
|||
*.~vsd
|
||||
|
||||
.vscode/
|
||||
.metals/
|
||||
.metals/
|
||||
.VSCodeCounter/
|
||||
|
|
|
@ -26,3 +26,4 @@ test_run_dir/
|
|||
# vscode
|
||||
.metals/
|
||||
.vscode/
|
||||
.VSCodeCounter/
|
||||
|
|
|
@ -5,6 +5,7 @@ import chisel3.util._
|
|||
import cpu.CpuConfig
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
import chisel3.util.experimental.BoringUtils
|
||||
|
||||
class ExecuteUnit extends Module {
|
||||
val io = IO(new Bundle {
|
||||
|
@ -22,6 +23,9 @@ class ExecuteUnit extends Module {
|
|||
val dataSram = new DataSram()
|
||||
})
|
||||
|
||||
val allow_to_go = io.ctrl.ctrlSignal.allow_to_go
|
||||
BoringUtils.addSource(allow_to_go, "exe_allow_to_go")
|
||||
|
||||
val valid = io.executeStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
|
||||
val fusel = io.executeStage.data.info.fusel
|
||||
|
||||
|
|
|
@ -115,9 +115,14 @@ class Lsu extends Module {
|
|||
)
|
||||
)
|
||||
|
||||
val allow_to_go = Wire(Bool())
|
||||
BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
|
||||
|
||||
val addr_last = RegEnable(addr, allow_to_go)
|
||||
|
||||
io.dataSram.en := valid && addr_aligned
|
||||
io.dataSram.wen := req_wmask & Fill(8, is_store)
|
||||
io.dataSram.addr := req_addr
|
||||
io.dataSram.addr := Mux(!allow_to_go, addr_last, req_addr) // 在mem被阻塞时,保持原先的读地址不变
|
||||
io.dataSram.wdata := req_wdata
|
||||
|
||||
val result = Wire(UInt(XLEN.W))
|
||||
|
|
2
difftest
2
difftest
|
@ -1 +1 @@
|
|||
Subproject commit be00525e85796bf0e8361c8d2de46ba57c460231
|
||||
Subproject commit 2d18d26d5c5f4f920184318462589b96ab4e1504
|
Loading…
Reference in New Issue